1. Field of the Invention
The present invention relates to the field of semiconductor processing and more particularly to a method and structure for increasing transistor density in an integrated circuit.
2. Description of the Relevant Art
Integrated circuits are widely employed in a variety of electronics applications to produce complex electronic circuits on an extremely small area of a monolithic semiconductor substrate, such as silicon. Universally recognized for their low cost, high speed, low power dissipation, and high reliability, semiconductor integrated circuits long ago replaced discrete components as the predominant and preferred electronic devices. World-wide sales of integrated circuits have increased exponentially since the early 1960""s. During this time, semiconductor manufacturers have engaged in a constant effort to reduce the cost and increase the complexity of integrated circuits by fabricating an ever larger number of transistors on a given area of semiconductor material. The predominant method of achieving greater circuit density has been the reduction of transistor geometries. Smaller transistors result in smaller and more complex devices. Small devices are desirable because of the increased number of devices manufacturable on a single semiconductor wafer and the increased probability that any individual device on a given silicon wafer will be free of random fatal defects. Since the early 1960s, when the average feature size or design rule within the industry was approximately 25 microns, the average design rule has decreased rather steadily by approximately 11% per year. The average design rule dropped below one micron in the mid 1980s, and has been decreasing steadily since that time.
In addition to the size of the transistors themselves, the amount of area required to isolate individual transistors from one another limits the transistor density, i.e., the number of transistors per unit area. Referring to FIG. 1, a conventional integrated circuit is shown in which a first transistor 10 and a second transistor 12 are fabricated on a semiconductor substrate 8. To isolate first transistor 10 from second transistor 12, an isolation structure such as shallow trench isolation structure 14 is required to prevent the inadvertent coupling of source/drain regions 16 of first transistor 10 and source/drain region 18 of second transistor 12. The lateral dimension dL of an isolation structure such as shallow trench isolation structure 14 limits the density of transistors that can be fabricated over a given area of substrate 8. As a rule of thumb, the minimum lateral dimension dL necessary to adequately ensure proper isolation between source/drain region 16 of first transistor 10 and source/drain region 18 of second transistor 12 is approximately equal to the lateral dimension Lt of first transistor 10 Shallow trench isolation structure 14 occupies a region of substrate 8 that could otherwise be devoted to the formation of active transistors and represents a limitation on the achievable transistor density. It would, therefore, be highly desirable to implement a circuit design and fabrication technique to reduce or eliminate the percentage of substrate 8 occupied by isolation regions 14.
The problems identified above are in large part addressed by an integrated circuit and semiconductor process for increasing the density of transistors within the integrated circuit. By fabricating transistors on multiple levels, the present invention advantageously reduces the area required to fabricate a given number of transistors.
Broadly speaking, the present invention contemplates a semiconductor process in which a dielectric layer is formed on an upper surface of a semiconductor substrate. An upper region of the semiconductor substrate includes a silicon base layer. Thereafter, an upper silicon layer is formed on an upper surface of the dielectric layer. The dielectric layer and the upper silicon layer are then patterned to form first and second silicon-dielectric stacks on the upper surface of the base silicon layer. The patterning of the dielectric layer and the upper silicon layer exposes portions of the silicon base layer that are not covered by the silicon-dielectric stacks. The first and second silicon-dielectric stacks are laterally displaced on either side of a channel region of the silicon substrate. The silicon-dielectric stacks each include a proximal sidewall and a distal sidewall. The proximal sidewalls are approximately coincident with respective boundaries of the channel region.
A gate dielectric layer is then formed on the exposed portions of the silicon base layer. Thereafter, proximal and distal spacer structures are formed on the proximal and distal sidewalls respectively of the first and second silicon-dielectric stacks. Each of the proximal spacer structures includes an interior sidewall in contact with the proximal sidewall of the silicon-dielectric stack. Portions of the first and second silicon-dielectric stacks located over respective source/drain regions of the base silicon layer are then selectively removed. The source/drain regions are laterally displaced on either side of the channel region and extend laterally from a position approximately coincident with a lateral position of the interior sidewall of the proximal spacer structure to a lateral position intermediate between the proximal spacer structure and its corresponding distal spacer structure.
Silicon is then deposited to fill first and second voids created by the selected removal of the first and second silicon-dielectric stacks. The silicon deposition also fills a silicon gate region above the gate dielectric over the channel region. Thereafter, an impurity distribution is introduced into the deposited silicon. The deposited silicon is then planarized to physically isolate the silicon within the gate region from the silicon within the first and second voids. The planarization and physical isolation of the deposited silicon result in the formation of a silicon gate structure and first and second source/drain structures.
In one embodiment, the semiconductor substrate includes a p-type epitaxial layer formed over a p+ silicon bulk. A preferred resistivity of the p-type epitaxial layer is in the range of approximately 10 to 15 xcexa9-cm. In one embodiment, the semiconductor substrate includes the silicon base layer. In another embodiment the silicon base layer is separated from the semiconductor substrate by an insulating layer. The formation of the dielectric layer preferably includes depositing oxide in a chemical vapor deposition reactor chamber maintained at a temperature in the range of approximately 300xc2x0 C. to 600xc2x0 C. at a pressure of less than approximately two torr. The formation of the upper silicon layer is accomplished, in a preferred embodiment, by thermally decomposing silane in a chemical vapor deposition reactor chamber maintained at a temperature in the range of approximately 580xc2x0 C. to 650xc2x0 C. and a pressure of less than approximately two torr.
The patterning of the dielectric layer and the upper silicon layer is suitably achieved by forming a photoresist mask over the upper silicon layer such that the photoresist mask exposes portions of the upper silicon layer that are aligned over the pair of source/drain regions. The exposed portions of the upper silicon layer are then etched in a reactive ion etcher and the portions of the dielectric layer aligned over the source/drain regions are etched in a reactive ion etcher.
The formation of the gate dielectric layer is preferably achieved by thermally oxidizing exposed portions of the base silicon layer in an oxygen bearing ambient maintained at a temperature in the range of approximately 700xc2x0 C. to 900xc2x0 C. The formation of the proximal and distal spacer structures preferably includes depositing a spacer material over a topography including a gate dielectric and the silicon-dielectric stacks and, thereafter, anisotropically etching the spacer material to remove the spacer material from regions of the topography that are substantially planar to the upper surface of the semiconductor substrate. The deposition of the spacer material preferably includes the step of depositing silicon nitride in a chemical vapor deposition reactor chamber maintained at a temperature of approximately 300xc2x0 C. to 900xc2x0 C. at a pressure of less than approximately two torr.
The selective removal of the portions of the first and second silicon-dielectric stacks preferably includes the steps of patterning a photoresist mask deposited on the silicon-dielectric stacks to expose regions of the first and second silicon-dielectric stacks that are aligned over the first and second source/drain regions respectively and etching the exposed portion of the silicon-dielectric stacks with a reactive ion etcher. The etching includes a first stage during which the upper silicon layer is etched and a second stage during which the dielectric layer is etched. The deposition of the silicon to fill the first and second voids is ideally accomplished by thermally decomposing silane in a chemical vapor deposition reactor chamber maintained at a temperature in the range of approximately 580xc2x0 C. to 650xc2x0 C. The introduction of the impurity distribution into the deposited silicon is accomplished by implanting impurity ions into the deposited silicon. In the preferred embodiment, the impurity ions are arsenic, phosphory, or boron. Ideally, the planarization of the deposited silicon is accomplished with a chemical mechanical polish.
The present invention further contemplates a semiconductor transistor which includes a silicon base layer, a gate dielectric formed on the silicon base layer, first and second silicon source/drain structures, first and second spacer structures and a silicon gate structure. The silicon base layer includes a channel region which is laterally displaced between a pair of source/drain regions. The gate dielectric is formed on the silicon base layer over the channel region. The first and second silicon source/drain structures are formed over the first and second source/drain regions respectively. Each of the silicon source/drain structures includes an interior sidewall that is laterally coincident with a lateral position of a respective boundary of the channel region. The first and second spacer structures are formed in contact with the interior sidewalls of the first and second silicon source/drain structures respectively. The silicon gate structure is formed between the first and second spacer structures above the gate dielectric over the channel region of the silicon base layer. The silicon gate structure includes an impurity distribution.
Preferably, the gate dielectric comprises a thermal oxide of approximately 20 to 50 angstroms in thickness. In one embodiment, the first and second silicon source/drain structures each include an impurity distribution and wherein a resistivity of the first and second silicon source/drain structures is less than approximately 500 xcexa9/square. In a presently preferred embodiment the first and second spacer structures are comprised of silicon nitride. A resistivity of the silicon gate structure is suitably less than approximately 500 xcexa9/square.
The present invention still further contemplates an integrated circuit. The integrated circuit includes a first transistor of the type described in the preceding paragraphs and an insulating layer formed above the first transistor. A second transistor according to the transistor described in the previous paragraphs is formed on the insulating layer wherein the second transistor is vertically displaced and electrically isolated from the first transistor.